1. Field of the Invention
The present invention relates to a data processing apparatus comprising a plurality of work registers, and more particularly to a data processing apparatus which can respond to an instruction for a processing by executing a process using a plurality of work registers.
2. Description of the Related Art
A data processing apparatus having a plurality of work registers called a general-purpose register can understand a variety of instructions. One such instruction can simultaneously designate two or more register operands. For example, a typical operation instruction according to a conventional architecture called RISC can simultaneously designate three registers. The three registers may include, with respect to an add operation instruction, two source registers and one destination register. With such an instruction, two values are retrieved from the two source registers to be added, and the operation result is then stored in the destination register. This method is referred to as a three-register-operand method. A two-register-operand method using an instruction designating two register operands for an operation is also known.
The three-register-operand method requires a fewer number of steps to execute certain operations as compared to the two-register-operand method. That is, when the two-register-operand method is used, one of the source registers is always overwritten by the operation result, which creates a need for one additional step. Specifically, if two or more operation instructions simultaneously designate the same value stored in the same register, that value may need to be first copied to another register before the respective operations are executed. An illustrative example is a case to execute a process in which two values are read from registers rs1 and rs2, respectively, to be used in a binomial operation, and the operation result is stored in a register rd. It is possible to designate the whole process using one instruction according to the three-register-operand method, while it is not possible according to the two-register-operand method. That is, with the two-register-operand method, two instructions are necessary to achieve the above; one for copying a value read from the register rs1 to the register rd, and the other for executing a binomial operation using the copied value and the value read from the register rs2 and storing the operating result in the register rd.
The three-register-operand method can effectively reduce the number of instructions, i.e., the number of cycles in which a concerned program is executed. However, an instruction according to this method is lengthy as it includes a larger number of operands than that of the two-register-operand method, which works against the common demand for shorter basic instructions. An example would be a case wherein a data processing apparatus comprising sixteen general-purpose registers employs a 16-bit instruction as a basic instruction. A field of 12 bits is used to designate three register operands, leaving a four-bit field available to contain encoded data regarding the types of an instruction or an operation. This field is, however, not sufficient to do so.
As a method free from the above problem and capable of designating a register operand using an instruction of a shorter length, Japanese Patent Application No. Hei 7-313146 discloses an instruction preparing method and a register designating method.
According to these methods, at least one register designation field consists of a fewer number of bits than other register designation fields. This shorter field is used to hold a register designation code, but not a register number itself used for explicit designation of a register. The register designation code is set corresponding to a register number by a correspondence table. By using m number of bits, 2m number of different register codes can be defined. In other words, 2m number of registers of all general-purpose registers can be indirectly designated through reference to a corresponding table.
An arrangement in which correspondence between a register designation code and a register number is dynamically changed as a program is being executed has also been proposed but, in general, a correspondence table is used, when a received instruction includes a certain register designation code as an operand, to determine the number of a register designated by the code so that the aimed work register is accessed. Conventionally, a structure for this type of process is achieved by means of, for example, hardware or firmware. Therefore, the register numbers set in the correspondence table are available only for reference, and are not available for use as data when executing a program. This is inconvenient for designers attempt to achieve more precise and flexible control over the data processing apparatus.
In particular, in a case where the content of the correspondence table is changed while a program is being executed, if an interrupt process is received, causing exceptional changes in the operating flow of the ongoing program, the content of the correspondence table which has been built up through the processing of the interrupted program, may be updated during the interrupt processing. Therefore, when the interrupted program is resumed upon completion of the interrupt processing, the correspondence table no longer has the same content as that immediately before the interruption. This may hinder returning to the operating flow.
Also, since all register numbers cannot be designated by register designation codes, selection must be made to determine which work registers are set accessible based on register designation codes. Conventionally, this selection is not always preferable in view of achieving effective processing.
The present invention has been conceived to overcome the above problems and aims to provide a data processing apparatus which is compatible with the three-register-operand method and which uses instructions reduced in length through employment of a register designation code. Particularly, this apparatus ensures high efficiency in executing a program, and properly resumes a program which was interrupted by other interrupt programs.
According to the present invention, there is provided a data processing apparatus using a stored-program method for executing an operation instructed by an instruction including a register designation code as an operand, comprising: a plurality of work registers identifiable by register numbers each of a typical number of bit length; and a correspondence table for holding at least one of the register numbers as designated register numbers in a state corresponding to register designation codes each of a less than the typical number of bits (standard bit number) and in a readable condition, the correspondence table being referred to by the data processing apparatus when executing the operation.
It may be preferable for the above data processing apparatus to further comprise register number obtaining section for obtaining the designated register number from the correspondence table.
Conventionally, the register numbers, set in the correspondence table and corresponding to register designation codes, are available only for reference so that the data processing apparatus can access a working register based on a register designation code. According to this invention, on the other hand, the register numbers held in the correspondence table can be read in response to, for example, an instruction included in a program, to be used as data.
Further, the above data processing apparatus further comprises designated register number storing section for storing the designated register number read from the correspondence table.
According to the present invention, when the operating flow is changed, such as branching from the main routine processing of the ongoing program to a different process, including a sub-routine or an interrupt or exception handler, the register numbers then held in the correspondence table which are relevant to the ongoing processing, are obtained from the table by the register number obtaining section, and stored in the designated register number storing section before beginning the different process.
With this arrangement, even if the content of the correspondence table should be updated during the interrupt processing, the designated register numbers relevant to the discontinued processing is not lost as is stored in the storing means during the interrupt processing.
A data processing apparatus as described above may further comprise designated register number returning section for returning the designated register number stored in the designated register number storing section back to the correspondence table.
According to the present invention, after the interrupt processing is completed, the content of the correspondence table stored in the storing section is returned to the correspondence table before the operating flow returns to the discontinued process to resume the processing.
With this arrangement, the discontinued processing can be resumed normally with the correspondence table holding the same content as that at the time of interruption.
In data processing according to the present invention, the designated register number storing section may store a number of the designated register numbers read from the correspondence table, and the designated register number returning section may then read the number of the designated register numbers from the designated register number storing section in the reverse order in which the number of the designated register numbers were stored in the register number storing section, and then return them to the correspondence table.
According to the present invention, even in a stepwise branching in which, for example, a process which interrupted a certain program is further interrupted by another process, the content of the table is stored to the designated register number storing means every branching. Further, a number of content of the table stored in the storing means are returned to the table in an inverse order to which they were stored, every time when the operating flow returns to the most recently interrupted process after the completion of the interrupt processing. That is, table content is stored and returned in an inverse order.
The above data processing apparatus may also execute specific processing, besides normal processing, in response to a process request supplied from either inside or outside thereof, and may further comprise designated register number updating section for updating the designated register number following a predetermined rule according to the execution of an instruction word; and correspondence table updating allowance/disallowance setting section for allowing or disallowing updating of the designated register number held in the correspondence table. In such a configuration, the designated register number storing section will store a process for storing the designated register number in response to the acceptance of the request for the specific processing, and the correspondence table updating allowance/disallowance setting section will disallow updating of the designated register number held in the correspondence table in a period covering the process for storing the designated register number.
The term xe2x80x9cnormal processingxe2x80x9d used here refers to, for example, main routine processing of a program. The term xe2x80x9cspecific processingxe2x80x9d refers to processing to which a normal processing branches, such as sub-routine processing or processing by an interrupt or exception handler program. A xe2x80x9cspecificxe2x80x9d case refers to any possible cases which should be handled with the content of a correspondence table stored elsewhere and the normal processing suspended, particularly, an interruption or exception occurring to a processor.
In this invention, when a xe2x80x9cspecificxe2x80x9d case occurs, the then content of the correspondence table is stored elsewhere. If the designated register number held in the table should be updated in the storing process, the storing processing may not be properly executed. In order to avoid abnormal storing processing, updating of the designated register numbers held in the correspondence table is disallowed at least during the storing process.
A data processing apparatus of the present invention may further comprise designated register number returning section for returning the designated register number after the completion of the specific processing, wherein the correspondence table updating allowance/disallowance setting section disallows updating of the designated register number held in the correspondence table over a period covering, not only the process for storing the designated register number, but also the process for returning the designated register numbers back to the correspondence table.
According to the present invention, the content of the correspondence table which was read from the table and stored elsewhere is returned to the table. If the designated register number held in the table should be updated in the returning process, that returning processing and another storing processing to be executed for another xe2x80x9cspecificxe2x80x9d case may not be performed properly. Therefore, the correspondence table updating allowance/disallowance setting section disallows updating of the designated register numbers not only during a storing process after a xe2x80x9cspecificxe2x80x9d case occurred, but also during a returning process for the operating flow to return to where the flow last branched.
Further, in the above data processing apparatus, the correspondence table may hold a predetermined number of register numbers in instruction words preceding a current instruction word which were designated as destination registers for storing results of the operation, and selected in an order of recent designation.
In general, an instruction includes a register operand for designating a source register which contains data to be used in an operation, and that for a destination register for storing data on the operation result. Which of a register number and a register designation code is used to designate a register in an instruction can be desirably determined. According to this invention, a predetermined number of designated destination register numbers are selected in an order of more recently designation, from those which were thus designated by current and preceding instructions, and set corresponding to register designation codes via the correspondence table.